Digital television chip, system and method thereof

ABSTRACT

A digital television chip having a reduced layout size is disclosed, comprising a multiplexer, and first and second converting units. The multiplexer, according to a control signal, outputs one of S-video signals SY and SC to the first converting unit, outputs the other of the S-video signals SY and SC to the second converting unit, outputs one of Tuner CVBS signals VIF and SIF to the first converting unit, outputs the other of the Tuner CVBS signals VIF and SIF to the second converting unit, or outputs a CVBS Line-in Video signal to one of the first and second converting units, for reducing the size of the chip. The first converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a first digital signal for signal processing. The second converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a second digital signal for signal processing.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/950,355, filed Jul. 18, 2007.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a layout size reduction method, and inparticular relates to a digital television chip receiving a plurality ofanalog signals and sharing one or more converting units to convert theplurality of analog signals into digital signals for reducing the sizeof the digital television chip.

2. Description of the Related Art

Digital television systems have become more popular given thetechnological development for high definition quality video images.Meanwhile, the digital television system generally receives differentkinds of analog signals, such as a VGA/YPbPr signal, S-video signals SYand SC, Tuner CVBS signals VIF and SIF and a CVBS Line-in Video signal.Thus, users can choose from any one of the previous mentioned analogsignals to display images on a digital television system.

BRIEF SUMMARY OF THE INVENTION

A detailed description is given in the following embodiments withreference to the accompanying drawings.

An embodiment of a digital television chip for converting analog signalsinto digital signals is provided. The digital television receives aVGA/YPbPr signal, a couple of S-video signals SY and SC, a couple ofTuner CVBS signals VIF and SIF and a CVBS Line-in Video signal. Thedigital television chip comprises a multiplexer, a first converting unitand a second converting unit.

The multiplexer receives the S-video signals SY and SC, the Tuner CVBSsignals VIF and SIF and the CVBS Line-in Video signal. Besides, themultiplexer, according to a control signal, outputs one of the S-videosignals SY and SC to the first converting unit, outputs the other of theS-video signals SY and SC to the second converting unit, outputs one ofthe Tuner CVBS signals VIF and SIF to the first converting unit, outputsthe other of the Tuner CVBS signals VIF and SIF to the second convertingunit, or outputs the CVBS Line-in Video signal to one of the first andsecond converting units.

The first converting unit converts one of the S-video signals SY and SC,one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Videosignal into a first digital signal for signal processing. The secondconverting unit converts unit converting one of the S-video signals SYand SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-inVideo signal into a second digital signal for signal processing.

Another embodiment of a digital television system is provided. Thedigital television system comprises a display for displaying images anda digital television chip for converting analog signals into the digitalsignals. The digital television chip receives a VGA/YPbPr signal, acouple of S-video signals SY and SC, a couple of Tuner CVBS signals VIFand SIF and a CVBS Line-in Video signal. The digital television chipcomprises a multiplexer, a first converting unit and a second convertingunit.

The multiplexer receives the S-video signals SY and SC, the Tuner CVBSsignals VIF and SIF and the CVBS Line-in Video signal. Besides, themultiplexer, according to a control signal, outputs one of the S-videosignals SY and SC to the first converting unit, outputs the other of theS-video signals SY and SC to the second converting unit, outputs one ofthe Tuner CVBS signals VIF and SIF to the first converting unit, outputsthe other of the Tuner CVBS signals VIF and SIF to the second convertingunit, or outputs the CVBS Line-in Video signal to one of the first andsecond converting units.

The first converting unit converts one of the S-video signals SY and SC,one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Videosignal into a first digital signal for signal processing. The secondconverting unit converts one of the S-video signals SY and SC, one ofthe Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signalinto a second digital signal for signal processing.

Another embodiment of a layout size reduction method by sharingconverting units for a digital television chip is provided. The methodcomprises using a multiplexer to receive a couple of S-video signals SYand SC, a couple of Tuner CVBS signals VIF and SIF and a CVBS Line-inVideo signal, outputting one of the S-video signals SY and SC, one ofthe Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal toa first converting unit according to a control signal, and outputtingthe other of the S-video signals SY and SC, the other of the Tuner CVBSsignals VIF and SIF, or the CVBS Line-in Video signal to a secondconverting unit according to the control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 is a block diagram of two chips of a digital television (DTV)system according to an embodiment of the invention; and

FIG. 2 is a block diagram of two chips of a digital television (DTV)system according to another embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carryingout the invention. This description is made for the purpose ofillustrating the general principles of the invention and should not betaken in a limiting sense. The scope of the invention is best determinedby reference to the appended claims.

In digital television systems, all CVBS (composite video bound signal)line-in/S-video/tuner CVBS signals are converted into digital signals byanalog front ends (AFE) and analog-to-digital converters (ADC). If CVBSline-in/S-video/tuner CVBS signals can share analog front ends (AFE) andanalog-to-digital converters, a digital television chip size for digitaltelevision systems can be reduced.

In digital television systems, a servo ADC detects a SCART input as aCVBS or RGB signal. The servo ADC also detects a voltage level of akey-pad of a controller. Since the servo ADC is a low speed ADC, theservo ADC can be replaced by other high speed ADCs, such as the ADCs forconverting CVBS line-in/S-video/tuner CVBS signals into correspondingdigital signals, to detect the SCART input or the RGB signal, during theavailable time period of the above high speed ADCs. Thus, the chip sizefor digital television systems can also be reduced a lot. In addition,the servo ADC may also have the following functions to detect whether aninput image is 4:3 an image or 16:9 an image, to adjust the tunerfrequency, to adjust the panel brightness according to the surroundingenvironmental brightness, or to detect input signal driving capacity.

For a two-chip solution of digital television systems, VGA/YPbPr signalsuse a high definition multimedia interface (HDMI) to transmit data. Ifwe only use VGA/YPbPr AFE 133, VGA/YPbPr ADC 123 and the HDMItransmitter 113 of the digital television system 100 to transmitVGA/YPbPr signals, CVBS line-in signal, S video signals or tuner CVBSsignals to a digital core chip 102, the size of the digital televisionchip 101 for digital television systems can be reduced a lot.

FIG. 1 is a block diagram of two chips of a digital television (DTV)system 100 according to an embodiment of the invention. The digitaltelevision system 100 comprises a digital television chip 101 forconverting analog signals into digital signals and a digital core chip102 for processing digital signals. The chip 101 comprises AFE units131, 132 and 133, ADC units 121, 122, 123, 124, 125 and 126, an HDMItransmitter 113, and a multiplexer 110. The chip 102 comprises a digitalcore 140 and an HDMI receiver 114. The function of the ADC units 121,122, 123, 124, 125 and 126 may be to convert analog signals into digitalsignals and the functions of the AFE units 131, 132 and 133 may be tofilter analog signals, adjust gains and DC voltage levels of analogsignals.

The ADC unit 121 and the AFE unit 131 form a first converting unit 171,The ADC unit 122 and the AFE unit 132 form a second converting unit 172,and the ADC unit 123 and AFE unit 133 form a third converting unit 173.In addition, the ADC unit 123 may be the VGA/YPbPr ADC unit, as shown inFIG. 1.

With regard to the CVBS line-in, signal VIDEO is processed by the AFEunit 131 and the ADC unit 121. With regard to S-video, signal SY isprocessed by the AFE unit 131 and the ADC unit 121 and signal SC isprocessed by the AFE unit 132 and the ADC unit 122. With regard to tunerCVBS, signal VIF is processed by the AFE unit 131 and the ADC unit 121and signal SIF is processed by the AFE unit 132 and the ADC unit 122.However, it is not limited that the first converting unit 171,comprising the AFE unit 131 and the ADC unit 121, converts the signalsSY, VIF or VIDEO and the second converting unit 172, comprising the AFEunit 132 and the ADC unit 122, converts the signal signals SC or SIF.The first converting unit 171 also can process the signals SC or SIF andthe second converting unit 172 also can process the signals SY, VIF orVIDEO. Any combination makes the signals SY and SC being converted bydifferent converting units and the signals VIF and SIF being convertedby different converting units applies. The main point is that CVBSline-in/S-video/tuner CVBS signals can share two AFE units 131 and 132and two ADC units 121 and 122 to decrease the number of AFE units andADC units. According to an embodiment of the invention, the ADC units121 and 122 use a 27 MHz reference clock and the ADC unit 123 uses a 170MHz reference clock.

The multiplexer 110 can select one of the following signals SY, VIF orVIDEO to output to the AFE unit 131 and the ADC unit 121 to convert intocorresponding digital signals and select one of the following signals SCor SIF to output to the AFE unit 132 and the ADC unit 122 to convertinto corresponding digital signals according to control signal Ctr1, asshown in FIG. 1. Thus, the size of chip 101 can be reduced. The ADCunits 121 and 122 output digital signals to the controller unit 130. Thecontroller unit 130 uses a control signal Ctr1 to control themultiplexer 110 to select one of the following signals SY, VIF or VIDEOand one of the following signals SC or SIF. Signal VGA/YPbPr isprocessed through the AFE unit 133, the ADC unit 123, the HDMI receiver113 and the HDMI transmitter 114 to the digital core 140. Signal SERVOADC INPUT is converted by a low speed ADC (servo ADC) 126 into acorresponding digital signal to be output to the digital core 140. Anantenna 161 receives RF signals to output to the digital tuner 162. Thedigital tuner 162 comprises a PGA (programmable gain amplifier) 163. TheRSSI ADC 124 receives the analog signals from the digital tuner 162 andconverts the analog signals into digital signals to output back to thedigital tuner 162 for adjusting gains by the PGA 163. The ADC 125receives the analog signals from digital tuner 162 and converts intodigital signals to output to the demodulation unit (DeMOD) 141 of thedigital core 140.

In another embodiment of the invention, the digital television system100 does not require the ADC unit 124. During free time periods(available time period) of the ADC 126, the low speed ADC 126 replacesthe RSSI ADC 124 to convert the analog signals from the digital tuner162 into digital signals for reducing the size of the chip.

In another embodiment of the invention, the digital television system100 does not require the ADC units 124 and 126. During free time periods(available time period) of the ADC unit 122 or 123, the ADC unit 122 or123 replaces both of the ADC units 124 and 126 to convert analog signalsinto digital signals for reducing the size of the chip.

In another embodiment of the invention, since the servo ADC 126 is a lowspeed ADC, the servo ADC 126 can be replaced by CVBS ADC 121, CVBS ADC122, or VGA/YPbPr ADC 123 during free time periods (available timeperiod).

FIG. 2 is a block diagram of two chips of a digital television (DTV)system 200 according to another embodiment of the invention. The digitaltelevision system 200 comprises a digital television chip 201 forconverting analog signals into digital signals and a digital core chip202 for processing digital signals. The chip 201 comprises AFE units231, 232 and 233, ADC units 221, 222, 223, 224 and 225, an HDMItransmitter 213, and a multiplexer 210. The chip 202 comprises a digitalcore 240 and an HDMI receiver 214. The function of the ADC units 221,222, 223, 224 and 225 may be to convert analog signals into digitalsignals and the functions of AFE units 231, 232 and 233 may be to filteranalog signals, adjust gains and DC voltage levels of analog signals.The ADC unit 221 and the AFE unit 231 form a first converting unit 271,the ADC unit 222 and the AFE unit 232 form a second converting unit 272,and the ADC unit 223 and the AFE unit 233 form a third converting unit273. In addition, the ADC unit 223 may be the VGA/YPbPr ADC unit, asshown in FIG. 2.

With regard to CVBS line-in, signal VIDEO is processed by a firstconverting unit 271 (AFE unit 231 and ADC unit 221). With regard toS-video, signal SY is processed by the first converting unit 271 (AFEunit 231 and ADC unit 221) and signal SC is processed by a secondconverting unit 272 (AFE unit 232 and ADC unit 222). With regard totuner CVBS, signal VIF is processed by the first converting unit 271(AFE unit 231 and ADC unit 221) and signal SIF is processed by thesecond converting unit 272 (AFE unit 232 and ADC unit 222). Signal SERVOADC INPUT is processed by a third converting unit 273 or the secondconverting unit 272 to be output to the digital core 240 according tocontrol signal Ctr2, especially during available time periods of thethird converting unit 273 or the second converting unit 272. The ADCunits 221 and 222 use a 27 MHz reference clock and the ADC 223 uses a170 MHz reference clock.

The multiplexer 210 can select one of the following signals SY, VIF orVIDEO to output to the AFE unit 231 and the ADC unit 221 and to convertinto corresponding digital signals and select one of the followingsignals SC, SIF or signal SERVO ADC INPUT to output to the AFE unit 232and ADC unit 222 to convert into corresponding digital signals accordingto a control signal Ctr2. Thus, the size of the chip 201 can be reduced.ADC units 221 and 222 output digital signals to a controller unit 230.The controller unit 230 uses the control signal Ctr2 to control themultiplexer 210 to select one of the following signals SY, VIF or VIDEOand one of the following signals SC, VIF or SERVO ADC INPUT. SignalVGA/YPbPr is processed through the AFE unit 233, the ADC unit 223, theHDMI transmitter 213 and the HDMI receiver 214 to the digital core 240.An antenna 261 receives RF signals to output to the digital tuner 262.The digital tuner 262 comprises a programmable gain amplifier (PGA) 263.The RSSI ADC 224 receives the analog signals from the digital tuner 262and converts analog signals into digital signals to output back to thedigital tuner 262 for gain adjustment by the programmable gain amplifier263. The ADC unit 225 receives the analog signals from the digital tuner262 to output to the demodulation unit 241 of the digital core 240 fordemodulation.

While the invention has been described by way of example and in terms ofpreferred embodiment, it is to be understood that the invention is notlimited to thereto. To the contrary, it is intended to cover variousmodifications and similar arrangements (as would be apparent to thoseskilled in the art). Therefore, the scope of the appended claims shouldbe accorded the broadest interpretation so as to encompass all suchmodifications and similar arrangements.

1. A digital television chip for converting analog signals into digitalsignals, wherein the digital television chip receives a couple ofS-video signals SY and SC, a couple of Tuner CVBS signals VIF and SIFand a CVBS Line-in Video signal, and the digital television chipcomprising: a multiplexer receiving the S-video signals SY and SC, theTuner CVBS signals VIF and SIF and the CVBS Line-in Video signal; afirst converting unit converting one of the S-video signals SY and SC,one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Videosignal into a first digital signal for signal processing; and a secondconverting unit converting one of the S-video signals SY and SC, one ofthe Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signalinto a second digital signal for signal processing; wherein themultiplexer, according to a control signal, outputs one of the S-videosignals SY and SC to the first converting unit, outputs the other of theS-video signals SY and SC to the second converting unit, outputs one ofthe Tuner CVBS signals VIF and SIF to the first converting unit, outputsthe other of the Tuner CVBS signals VIF and SIF to the second convertingunit, or outputs the CVBS Line-in Video signal to one of the first andsecond converting units.
 2. The digital television chip as claimed inclaim 1, wherein the first converting unit comprises a first AFE unitfor filtering signals adjusting gains or adjusting DC voltage levels anda first ADC unit for converting analog signals into the first digitalsignal and the second converting unit comprises a second AFE unit forfiltering signals, adjusting gains or adjusting DC voltage levels and asecond ADC unit for converting analog signals into the second digitalsignal.
 3. The digital television chip as claimed in claim 1, furthercomprising a third converting unit and an HDMI transmitter, wherein thethird converting unit receives a VGA/YPbPr signal and converts theVGA/YPbPr signal into a third digital signal to output to the HDMItransmitter.
 4. The digital television chip as claimed in claim 3,wherein the third converting unit comprises a third AFE for filteringsignals, adjusting gains or DC voltage levels and a third ADC unit forconverting analog signals into digital signals.
 5. The digitaltelevision chip as claimed in claim 1, wherein the control signal issent by a digital core chip to control the multiplexer to output one ofthe S-video signal SY, the Tuner CVBS signal VIF and the CVBS Line-inVideo signal to the first converting unit and output one of the S-videosignal SC and the Tuner CVBS signal SIF to the second converting unit.6. The digital television chip as claimed in claim 1, wherein thedigital television chip is coupled to a digital tuner, the digital tunerreceives a signal from an antenna, adjusts its gain by an insideprogrammable gain amplifier and an outside fourth ADC unit, and outputsthe adjusted signal to a fifth ADC unit for conversion of the adjustedsignal into a fourth digital signal to output to a digital core chip. 7.The digital television chip as claimed in claim 6, wherein the digitalcore chip comprises a demodulation unit for receiving the fourth digitalsignal.
 8. The digital television chip as claimed in claim 1, whereinthe multiplexer further receives a SERVO ADC INPUT signal, and when thesecond converting unit is at an available time period, the multiplexeroutputs the SERVO ADC INPUT signal to the second converting unit forconversion into digital signals to output to a digital core chip or whenthe third converting unit is at an available time period, themultiplexer outputs the SERVO ADC INPUT signal to the third convertingunit for conversion into digital signals to output to the digital corechip.
 9. A digital television system, comprising: a display fordisplaying images; and a digital television chip for converting analogsignals into digital signals, wherein the digital television chipreceives a couple of S-video signals SY and SC, a couple of Tuner CVBSsignals VIF and SIF and a CVBS Line-in Video signal, comprising: amultiplexer receiving the S-video signals SY and SC, the Tuner CVBSsignals VIF and SIF and the CVBS Line-in Video signal; a firstconverting unit converting one of the S-video signals SY and SC, one ofthe Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signalinto a first digital signal for signal processing; and a secondconverting unit converting one of the S-video signals SY and SC, one ofthe Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signalinto a second digital signal for signal processing; wherein themultiplexer, according to a control signal, outputs one of the S-videosignals SY and SC to the first converting unit, outputs the other of theS-video signals SY and SC to the second converting unit, outputs one ofthe Tuner CVBS signals VIF and SIF to the first converting unit, outputsthe other of the Tuner CVBS signals VIF and SIF to the second convertingunit, or outputs the CVBS Line-in Video signal to one of the first andsecond converting units.
 10. The digital television system as claimed inclaim 9, wherein the first converting unit comprises a first AFE unitfor filtering signal, adjusting gains or adjusting DC voltage levels anda first ADC unit for converting analog signals into the first digitalsignal and the second converting unit comprises a second AFE unit forfiltering signal, adjusting gains or adjusting DC voltage levels and asecond ADC unit for converting analog signals into the second digitalsignal.
 11. The digital television system as claimed in claim 9, furthercomprising a third converting unit and an HDMI transmitter, wherein thethird converting unit receives a VGA/YPbPr signal and converts theVGA/YPbPr signal into a third digital signal to output to the HDMItransmitter.
 12. The digital television system as claimed in claim 11,wherein the third converting unit comprises a third AFE for filteringsignal, adjusting gains or adjusting DC voltage levels and a third ADCunit for converting analog signals into digital signals.
 13. The digitaltelevision system as claimed in claim 9, wherein the control signal issent by a digital core chip to control the multiplexer to output one ofthe S-video signal SY, the Tuner CVBS signal VIF and the CVBS Line-inVideo signal to the first converting unit and output one of the S-videosignal SC and the Tuner CVBS signal SIF to the second converting unit.14. The digital television system as claimed in claim 9, wherein thedigital television system is coupled to a digital tuner, the digitaltuner receives a signal from an antenna, adjusts its gains by an insideprogrammable gain amplifier and an outside fourth ADC unit and outputsthe adjusted signal to a fifth ADC unit for conversion into a fourthdigital signal to output to a digital core chip.
 15. The digitaltelevision system as claimed in claim 14, wherein the digital core chipcomprises a demodulation unit for receiving the fourth digital signal.16. The digital television system as claimed in claim 9, wherein themultiplexer further receives a SERVO ADC INPUT signal, and when thesecond converting unit is at an available time period, the multiplexeroutputs the SERVO ADC INPUT signal to the second converting unit forconversion into digital signals to output to a digital core chip or whenthe third converting unit is at an available time period, themultiplexer outputs the SERVO ADC INPUT signal to the third convertingunit for conversion into digital signals to output to the digital corechip.
 17. A layout size reduction method by sharing converting units fora digital television chip, comprising: using a multiplexer to receive acouple of S-video signals SY and SC, a couple of Tuner CVBS signals VIFand SIF and a CVBS Line-in Video signal; outputting one of the S-videosignals SY and SC, one of the Tuner CVBS signals VIF and SIF, or theCVBS Line-in Video signal to a first converting unit according to acontrol signal; and outputting the other of the S-video signals SY andSC, the other of the Tuner CVBS signals VIF and SIF, or the CVBS Line-inVideo signal to a second converting unit according to the controlsignal.
 18. The layout size reduction method as claimed in claim 17,wherein the multiplexer is used to switch output of the signals toreduce a number of required converting units to reduce chip size. 19.The layout size reduction method as claimed in claim 17, wherein thefirst converting unit converts one of the S-video signal SY, the TunerCVBS signal VIF and the CVBS Line-in Video signal into a first digitalsignal for signal processing, and the second converting unit convertsone of the S-video signal SC and the Tuner CVBS signal SIF into a seconddigital signal for signal processing.